Job Description

The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide targeted support to mixed-signal High-Bandwidth Memory (HBM) and DDR PHY IP customers. We are looking for a candidate to join the team to help with front-end tasks. The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

• ASIC RTL design and verification at chip level and/or block level
• Solid Verilog, PERL, TCL and Python skills
• Understanding of static timing analysis and synthesis, DFT/ATPG skills would be a plus
• Knowledge of any high-speed communication protocol is not mandatory but an asset
• Previous knowledge in customer support and/or silicon bring-up is a plus

The diversity of tasks allow each team member to develop new skills and learn about all aspects of our PHY design. The main focus of the team is to support the application engineers solving customer problems, usually requiring deep investigations into the design. When not working on customer questions we use our knowledge to drive product improvements. Experience with HBM or DDR protocols is a definite asset but not mandatory. Your tasks will be adapted to your skills and development and will include some or all listed below:

• Generate test benches and test cases
• Perform RTL and gate-level SDF-annotated simulations and debug
• May perform mixed-signal (digital + analog) simulations and debug
• Interact with our application engineers and/or customers. Provide guidance to customers on HBM/DDR PHY front-end related (e.g. simulation, firmware, software, evaluation board) aspects
• Participate in the generation of data books, application notes, and white papers
• Other related duties as assigned by the manager

Key Qualifications

• BSEE degree or Applied Science degree (or equivalent) with 8+ years of related experience
• Excellent communication and presentation skills

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

The base salary range across the U.S. for this role is between $135,000-$203,000. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education

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At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

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